tsdoi10.1109/ASPDAC.2018.8297293

tsunitThe Hong Kong University of Science and Technology (HKUST)

tsjournalname23rd Asia and South Pacific Design Automation Conference (ASP-DAC, CCF-C)

tsprojectsourceThis work is partially supported by Hong Kong Research Grant Council (RGC) under Grant 619813.

tskeywordConvolutional Neural Network (CNN), data encoding, dynamic quantization, computation saving

tssummaryTo solve the scaling, memory wall and high power density issues, recently RRAM-based accelerators, which show a better energy and area efficiency compared with the CMOSbased counterparts, have been proposed for convolutional neural networks. However, the RRAM-based architectures still face several design challenges, including the high energy and timing overhead at the analog/digital (A/D) conversion and interfacing circuits. To address these issues, we propose several novel optimization schemes in this work. First an encoding scheme for the synaptic weights and the input feature maps is proposed to reduce the energy of the in-situ computation and the bit-resolution of the A/D conversion. Then the resolution of the A/D conversion is further optimized for a lower energy consumption. Moreover, a dynamic quantization scheme for the multiply-accumulate operations (MACs) is proposed to improve the throughput and the energy efficiency by reducing the number of partial products. Experimental results show that the throughput, the energy efficiency and the area efficiency are improved by 2 to 4 times when compared with the state-of-the-art RRAM-based accelerators.

tsremarkCCF-C

tsauthorsJingbo Jiang,Jingyang Zhu,Chi-Ying Tsui

tsfirstauthorXizi Chen

tstranslationno

tspublishtime2018-01-01