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Xizi Chen

Supervisor of Master's Candidates
Name (Simplified Chinese):Xizi Chen
Name (English):Xizi Chen
Name (Pinyin):chenxizi
Administrative Position:专任教师
Academic Titles:专任教师
Professional Title:Associate researcher
Status:Employed
Education Level:博士
Degree:Doctoral degree
Business Address:华中农业大学第一综合楼B座413
E-Mail:
Alma Mater:The Hong Kong University of Science and Technology
Teacher College:College of Informatics
School/Department:Huazhong Agricultural University
Discipline:Computer Architecture    Computer Applications Technology    
Other Contact Information:

PostalAddress:

Email:

Profile

基本信息

姓名:    陈夕子 

学位:    博士

职称:    副研究员            

联系方式:QQ - 1606860281

邮箱:    xchenbn@mail.hzau.edu.cn

单位:    华中农业大学 信息学院


教育经历

2011.09 - 2015.06:  西安交通大学(XJTU),电子科学与技术,工学学士

2015.09 - 2021.06:  香港科技大学(HKUST),电子及计算机工程,哲学博士


主要职历

2019.09 - 2021.01:  香港科技大学,电子及计算机工程系,研究助理

2021.07 - 至今:  华中农业大学,信息学院,副研究员,硕士生导师(计算机科学与技术、电子信息)


招生专业

      计算机科学与技术、电子信息等


研究方向

       深度学习算法与计算架构、人工智能芯片等


研究情况

      目前主要从事深度学习算法及架构设计、人工智能芯片等相关方向的研究,近年来研究成果在 CCF-A 类 TCAD(2023)、

DAC(2023、2020),CCF-B 类 DATE、CCF-C 类 Integration, the VLSI Journal、 ASP-DAC 及 VLSI-SoC、AICAS 等

人工智能和AI芯片领域重要的国际期刊与会议上发表十余篇,在 DAC(San Francisco, USA)、ASP-DAC (Tokyo, Japan)、

ASP-DAC(Jeju, South Korea)等国际会议上做大会报告。

      主持国家自然科学基金青年基金项目1项、湖北省自然科学基金青年项目1项、中央高校基本科研业务费专项基金1项,

参与国家自然科学基金面上项目1项,获得2021年“武汉英才” 优秀青年人才项目1项,担任 CCF YOCSEF 武汉委员、

SCI 期刊 PLOS ONE 学术编辑(Academic Editor)、IEA/AIE 程序委员会成员(TPC Member),IEEE TCAS I、

IEEE SPL、IEEE Access、IEEE TCE、JCST 等 SCI 期刊审稿人。

      欢迎对深度学习算法及计算架构、人工智能芯片等相关领域感兴趣的同学与我联系。(QQ - 1606860281)


[1] Xizi Chen#*, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui. Tight Compression: Compressing CNN Through Fine-

Grained Pruning and Weight Permutation for Efficient Implementation. IEEE Transactions on Computer-Aided 

Design of Integrated Circuits and Systems, vol. 42, no. 2, pp. 644-657, 2023.  (CCF-A) 

[2] Xizi Chen#*, Rui Pan, Xiaomeng Wang, Fengshi Tian, Chi-Ying Tsui, Late Breaking Results: Weight Decay is ALL 

You Need for Neural Network Sparsification. 2023 60th ACM/IEEE Design Automation Conference (DAC), San 

Francisco, CA, USA, 2023, pp. 1-2.   (CCF-A)

[3] Xizi Chen#*, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui. Tight Compression: Compressing CNN Model Tightly 

Through Unstructured Pruning and Simulated Annealing Based Permutation. 57th Design Automation Conference 

(DAC), San Francisco, USA. July 20-24, 2020, 1-6.  (CCF-A)

[4] Jingbo Jiang#, Xizi Chen*, Chi-Ying Tsui, Accelerating Large Kernel Convolutions with Nested Winograd 

Transformation. 2023 IFIP/IEEE 31st International Conference on Very Large ScaleIntegration (VLSI-SoC), Dubai, 

United Arab Emirates, 2023, pp. 1-6. 

[5] Xizi Chen*#, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui. CompRRAE: RRAM-Based Convolutional Neural Network 

Accelerator with Reduced Computations Through a Runtime Activation Estimation. 24th Asia and South Pacific 

Design Automation Conference (ASP-DAC), Tokyo, Japan. Jan 21-24, 2019, 133-139.  (CCF-C)

[6] Xizi Chen#*, Jingbo Jiang, Jingyang Zhu, Chi-Ying Tsui. SubMac: Exploiting the Subword-Based Computation in 

RRAM-Based CNN Accelerator for Energy Saving and Speedup. Integration, the VLSI Journal, 2019, 69: 356-368. 

(CCF-C)

[7] Xizi Chen#*, Jingbo Jiang, Jingyang Zhu, Chi-Ying Tsui. A High-Throughput and Energy-Efficient RRAM-Based 

Convolutional Neural Network Using Data Encoding and Dynamic Quantization. 23rd Asia and South Pacific 

Design Automation Conference (ASP-DAC), Jeju, Korea. Jan 22-25, 2018, 123-128. (CCF-C)

[8] Jingyang Zhu#*, Jingbo Jiang, Xizi Chen, Chi-Ying Tsui. SparseNN: An Energy-Efficient Neural Network Accelerator 

Exploiting Input and Output Sparsity. Design, Automation and Test in Europe Conference and Exhibition (DATE), 

Dresden, Germany. March 19-23, 2018, 241-244. (CCF-B)

[9] Xiaomeng Wang#*, Xuejiao Liu, Xianghong Hu, Xiaopeng Zhong, Xizi Chen, Yu Liu, Patrick Kong, Fengshi Tian, 

Chiying Tsui, TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting 

Multibit Matrix-Vector Multiplication for Binarized Neural Network. 2022 IEEE 4th International Conference 

on Artificial Intelligence Circuits and Systems (AICAS), Incheon, Korea, Republic of, 2022, pp. 66-69.

[10] Xiaomeng Wang#*, Fengshi Tian, Xizi Chen, Jiakun Zheng, Xuejiao Liu, Fengbin Tu, Jie Yang, Mohamad Sawan, 

Kwang-Ting (Tim) Cheng, Chi-Ying Tsui. A 137.5 TOPS/W SRAM Compute-in-Memory Macro with 9-b Memory 

Cell-Embedded ADCs and Signal Margin Enhancement Techniques for AI Edge Applications. arXiv:2307.05944, 

pp. 1-3.


2025~2027: 国家自然科学基金青年基金项目,“支持片上神经结构自适应优化的端侧训练芯片研究”,主持

2024~2026: 湖北省自然科学基金青年项目,“神经网络稀疏生长与加速芯片研究”,主持

2022~2024: 华中农业大学自主科技创新基金项目:“深度学习算法及硬件架构一体化研究”,主持

2021年:        武汉英才” 优秀青年人才

2015~2018: Hong Kong PhD Fellowship


学术兼职

      SCI 期刊 PLOS ONE 学术编辑(Academic Editor),IEEE TCAS I、IEEE SPL、IEEE Access、IEEE TCE、JCST 等 SCI 

期刊审稿人,IEEE TCAS-I、IEEE ACCESS、IEA/AIE 程序委员会成员(TPC Member)


Educational Experience

[1] 2015.9——2021.6
The Hong Kong University of Science and Technology > Electronic and Computer Engineering > Doctoral degree
[2] 2011.9——2015.6
Xi'an Jiaotong University > Electronic Science and Technology > Bachelor's Degree

Work Experience

[1] 2021.7-Now
华中农业大学 > 信息学院 > 专任教师
[2] 2019.9-2021.1
The Hong Kong University of Science and Technology > Department of Electronic and Computer Engineering > Part-Time Research Assistant

Social Affiliations

[1] 

PLOS ONE,  Academic Editor

[2] 

IEEE Signal Processing Letters 审稿人

[3] 

CCF YOCSEF武汉委员

[4] 

Reviewer of IEEE Transactions on Circuits and Systems I (TCAS-I)

[5] 

IEEE Access 审稿人

[6] 

IEEE Transactions on Consumer Electronics (IEEE TCE) 审稿人

[7] 

Reviewer of Journal of Computer Science and Technology (JCST)

[8] 

36th IEA/AIE 程序委员会成员(TPC Member)

Research Group
Name of Research Group:机器学习与计算机视觉

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