DOI码：10.23919/DATE.2018.8342010

所属单位：Hong Kong University of Science and Technology (HKUST)

发表刊物：Design, Automation and Test in Europe Conference and Exhibition (DATE，CCF-B类)

关键字：Neural networks, training, sparsity, computer architecture, scheduling, prediction algorithms

摘要：Contemporary Deep Neural Network (DNN) contains millions of synaptic connections with tens to hundreds of layers. The large computational complexity poses a challenge to the hardware design. In this work, we leverage the intrinsic activation sparsity of DNN to substantially reduce the execution cycles and the energy consumption. An end-to-end training algorithm is proposed to develop a lightweight (less than 5% overhead) run-time predictor for the output activation sparsity on the fly. Furthermore, an energy-efficient hardware architecture, SparseNN, is proposed to exploit both the input and output sparsity. SparseNN is a scalable architecture with distributed memories and processing elements connected through a dedicated on-chip network. Compared with the state-of-the-art accelerators which only exploit the input sparsity, SparseNN can achieve a 10%-70% improvement in throughput and a power reduction of around 50%.

备注：中国计算机学会 CCF-B 类

合写作者：Jingbo Jiang,Xizi Chen,Chi-Ying Tsui

第一作者：Jingyang Zhu

是否译文：否

发表时间：2018-01-01